SS Stepper Controller v1.1 · WaveForge / StabilityCore · ordered 2026-09-17

5-Axis Level Shifter — Board Map

The clean board. No hand modifications, no flying jumpers, the ESP32 seats directly. Supersedes v1.0, which stays in service as a tester.

The board

SS Stepper Controller v1.1 board map with all reference designators and test points labeled
120 × 80 mm, 2 layer. J1 at left, four buffers centre, five driver terminals around the edges. R1–R11 and C1–C4 are on the underside. Flux 3D view, top, with J1 selected (green outline).

What to read off it before you touch anything:

Connectors

RefWhatPositionsDrill
J1ESP32 DevKit, 30-pin, USB to the left2×15 @ 2.54 mm, rows 25.4 mm1.0 mm
J2Power in — +5V and GND2 @ 5.08 mm1.5 mm
J3Driver B6 @ 5.08 mm — PUL+ PUL− DIR+ DIR− ENA+ ENA−1.5 mm
J4Driver A
J5Driver C
J6Driver D
J8Driver E — yaw (new in v1.1)
J7Bench ground3 @ 5.08 mm, all GND1.5 mm
The returns come home now. v1.0 carried only PUL+ and DIR+, so every PUL−/DIR− had to land on a separate bus (J11) — which turned out never to be connected to ground. Each terminal now carries its own returns beside its own signals, and J11 is gone. Six wires, one connector, per axis.

ESP32 pin assignment

GPIOSignalBufferTerminalTest pt
25STEP AIC1 A/BJ4 PUL+TP1
26DIR AJ4 DIR+TP2
27STEP BJ3 PUL+TP3
32DIR BJ3 DIR+TP4
33STEP CIC2 C/DJ5 PUL+TP5
18DIR CJ5 DIR+TP6
19STEP DJ6 PUL+TP7
23DIR DJ6 DIR+TP8
14STEP E — yawIC4 E/yawJ8 PUL+TP10
13DIR E — yawJ8 DIR+TP11
21ENABLE, all fiveIC3 ×4 + IC4 ×1every ENA+TP9
⚠ GPIO 16 and 17 are reserved and are NOT on this board. They carry the pitch and roll servo PWM, which connects straight to the ESP32. They were moved there from 32 and 33, which the level shifter needs for DIR B and STEP C — a collision caught on 2026-09-17 before this board was fabricated. ⛔ Also avoid GPIO 0, 2, 12 and 15 (boot strapping); 34/35/36/39 are input-only; 6–11 are flash. GPIO 4 and 22 remain spare.

Buffers and passives

RefPartChannels used
IC1SN74AHCT125N4 — STEP/DIR A and B
IC2SN74AHCT125N4 — STEP/DIR C and D
IC3SN74AHCT125N4 — ENA A, B, C, D
IC4SN74AHCT125N3 — STEP E, DIR E, ENA E  (1 spare)
R1–R111 k 0805pull-down, one per buffer-input net
C1–C40.1 µF 0805decoupling, pins 14–7, one per chip
Why eleven resistors and not fifteen. All five ENA buffer inputs sit on one GPIO21 net, so it is electrically one node and takes one pull-down. Five in parallel would make a 200 Ω pull-down and load that pin with 16.5 mA, near the ESP32's per-pin limit. Why 1 k and not 10 k: measured on v1.0, a 10 k only pulled the input to about 1 V — inside the indeterminate band for AHCT. 1 k lands near 0.1 V and costs the ESP32 3.3 mA. What they are for: the inputs float high whenever the ESP32 is unplugged, reset or reflashing, and the board has no other way to define them.

Pin 1 markers — what this board has and what it doesn’t

From the Gerber apertures, 2026-09-17. This is the copper, not the render.

PartPadsPin 1 marker?What that means on the bench
IC1–IC4 sockets13 oval + 1 rect each✅ yes — rectangular pad, bottom-leftNotch LEFT. Count 1→7 right along the bottom, 8→14 left along the top.
J2 power in1 round + 1 rect✅ yesSquare pad is pin 1.
3-pin connector2 round + 1 rect✅ yesSquare pad is pin 1.
J1 ESP32 header30 identical ovalsnoneThe silkscreen “USB LEFT” is the only orientation cue. Run the continuity checks below before seating a module.
J3–J6, J8 terminals30 identical 2.3 mm roundsnoneNo pin 1 anywhere on the five 6-pin blocks. Go by the silkscreen labels and confirm by tracing.
v1.2 list: add a square pad at J1 pin 1, and one at pin 1 of each terminal block. The chips got the treatment and the connectors did not — and the connectors are the ones that can be inserted backwards.

Assembly order

  1. Measure a terminal header pin first. Holes are 1.5 mm; the pluggable Phoenix-style part must clear that, and there must be nothing under the header but six pins in a line.
  2. Underside passives before anything else — R1–R11 and C1–C4 are on the bottom and get awkward once tall parts are on the top.
  3. DIP sockets, four of them. Orient by the board silkscreen notch.
  4. J1 headers — two single-row 1×15 female strips, not a dual-row part. Push both onto the ESP32's pins first so the module holds them square, drop the assembly into the board, tack the corners, check it sits flat, then solder the rest.
  5. Terminals J2 through J8.
  6. Verify before the chips go in. Flash the pin walker, hold each signal, and meter its terminal — now far easier, since TP1–TP11 give you a pad per signal instead of a screw head.
  7. Then one motor, lowest current, loose on the bench, nothing coupled to the frame.

★ The verified map — straight from the IPC-D-356 netlist

Read 2026-09-17 from esp32-stepper-level-shifter.d356, parsing 317 and 327 records. This is the manufacturing data, not the schematic and not the render. Use it as the answer key for the bare-board tracing below — trace first, then check.

SS Stepper Controller v1.1 bare board pad layout with silkscreen
Bare-board view — pads and silkscreen, no components. The bench reference. Note the square pin 1 pad at the bottom-left of each socket, and that J1’s thirty pads are all identical.

Buffer channels — which channel carries which signal

ChipChInOutSignalGoes toIn ✓Out ✓
IC1123STEP_A · GPIO 25J4 PUL+
IC1256DIR_A · GPIO 26J4 DIR+
IC1398STEP_B · GPIO 27J3 PUL+
IC141211DIR_B · GPIO 32J3 DIR+
IC2123STEP_C · GPIO 33J5 PUL+
IC2256DIR_C · GPIO 18J5 DIR+
IC2398STEP_D · GPIO 19J6 PUL+
IC241211DIR_D · GPIO 23J6 DIR+
IC3123ENABLE · GPIO 21J3 ENA+
IC3256ENABLE · GPIO 21J4 ENA+
IC3398ENABLE · GPIO 21J5 ENA+
IC341211ENABLE · GPIO 21J6 ENA+
IC4123STEP_E · GPIO 14J8 PUL+
IC4256DIR_E · GPIO 13J8 DIR+
IC4398ENABLE · GPIO 21J8 ENA+
IC441211tied to GNDno connection

On all four chips OE pins 1, 4, 10 and 13 go to GND (outputs permanently enabled — there is no tri-state on this board), pin 14 = 5V, pin 7 = GND. IC3’s four inputs are all on the one ENABLE_IN net, which is the design intent. IC4 channel 4 is a terminated spare — its input is tied to GND rather than left floating, and its output goes nowhere. That is better practice than leaving it open.

J1 — all thirty pads

⚠️ Counting convention, stated once so it cannot drift: the silkscreen says J1 ESP32 / USB LEFT, so position 1 is the LEFTMOST pad, at the USB end, counting left → right in each row. Upper and lower rows, not columns.

UPPER row (the DevKit’s VIN side)
PosDevKitNetGPIO
1VIN5V
2GNDGND
313DIR_EGPIO 13
412— not connected —
514STEP_EGPIO 14
627STEP_BGPIO 27
726DIR_AGPIO 26
825STEP_AGPIO 25
933STEP_CGPIO 33
1032DIR_BGPIO 32
1135— not connected —
1234— not connected —
13VN— not connected —
14VP— not connected —
15EN— not connected —
LOWER row (the DevKit’s 3V3 side)
PosDevKitNetGPIO
13V3— not connected —
2GNDGND
315— not connected —
42— not connected —
54— not connected —
6RX2— not connected —
7TX2— not connected —
85— not connected —
918DIR_CGPIO 18
1019STEP_DGPIO 19
1121ENABLEGPIO 21
12RX0— not connected —
13TX0— not connected —
1422— not connected —
1523DIR_DGPIO 23
Three independent things agree on the orientation, which is why this one can be trusted where v1.0’s could not:
  1. The silkscreen says USB LEFT.
  2. The netlist puts 5V at upper position 1 and GND at position 2 of both rows — and VIN / 3V3 are the USB-end pins on a 30-pin DevKit.
  3. The full thirty-pad sequence matches the stock DOIT V1 pinout exactly, in order, including every unused pin — VIN, GND, 13, 12, 14, 27, 26, 25, 33, 32, 35, 34, VN, VP, EN on the upper row and 3V3, GND, 15, 2, 4, RX2, TX2, 5, 18, 19, 21, RX0, TX0, 22, 23 on the lower.
⚠️ GND is not unique — position 2 in both rows — so finding a ground does not by itself tell you which row you are on. 5V at upper position 1 is the unique landmark.

★ Verify the bare board first — before any part is soldered

Do this on a bare board, cold, with nothing fitted. Every pad is reachable from both sides, nothing is in the way, and continuity means what it says because there is no semiconductor anywhere in the path. You have three boards — keep one permanently bare as the tracer. That is what made the v1.0 verification possible without disturbing a working assembly.

Why bother, when the schematic says it is right? Because on v1.0 the documentation and the copper disagreed, and the copper won. Two of eight channels were mapped wrong, and a "ground bus confirmed by continuity" turned out to read 100 kΩ to ground — which would have killed all four axes while every terminal measured correctly. This board has never been tested at all. Continuity on bare copper is the only thing that has never lied.

The method, per channel. An SN74AHCT125 is four independent buffers. Socket input pad → J1 gives you which ESP32 pin drives it. Socket output pad → screw terminal gives you which signal it becomes. Counting the socket pins on THIS board — verified 2026-09-17 from the Gerbers, not the render: each socket has exactly one rectangular pad (aperture D16, 1.5 × 2.0 mm) and thirteen ovals; 4 squares and 52 ovals board-wide, which is 14 × 4 with no exceptions. That square pad is pin 1. All four sit at the bottom-left, and the chips run horizontally (pads span 15.24 mm in X, rows 7.62 mm apart). So: the notch faces LEFT, pin 1 is bottom-left, count 1→7 rightward along the bottom row, then 8→14 leftward along the top row. ⚠ An earlier draft of this page said “notch at the top, pin 1 top-left, count down the left” — that is the vertical orientation and is wrong for this board. It would have you counting the wrong way around the socket, which is exactly how v1.0 ended up 2-of-8 wrong. Confirm every beep by lifting a probe and hearing it stop — a probe tip bridging two adjacent pads gives a false hit, and that is what caused the pad 18-vs-19 mix-up on v1.0.

ChipChInOutChip’s signal setInput traces to…Output traces to…
IC1123STEP A · DIR A · STEP B · DIR B
→ J4 PUL+ / DIR+ · J3 PUL+ / DIR+
☐ J1 pad ____ = GPIO ____☐ ____________
IC1256☐ J1 pad ____ = GPIO ____☐ ____________
IC1398☐ J1 pad ____ = GPIO ____☐ ____________
IC141211☐ J1 pad ____ = GPIO ____☐ ____________
IC2123STEP C · DIR C · STEP D · DIR D
→ J5 PUL+ / DIR+ · J6 PUL+ / DIR+
☐ J1 pad ____ = GPIO ____☐ ____________
IC2256☐ J1 pad ____ = GPIO ____☐ ____________
IC2398☐ J1 pad ____ = GPIO ____☐ ____________
IC241211☐ J1 pad ____ = GPIO ____☐ ____________
IC3123GPIO21 ENA — all four
→ ENA+ on J3, J4, J5, J6
☐ J1 pad ____ = GPIO ____☐ ____________
IC3256☐ J1 pad ____ = GPIO ____☐ ____________
IC3398☐ J1 pad ____ = GPIO ____☐ ____________
IC341211☐ J1 pad ____ = GPIO ____☐ ____________
IC4123STEP E · DIR E · GPIO21 ENA · 1 spare
→ J8 PUL+ / DIR+ / ENA+ · 1 unused
☐ J1 pad ____ = GPIO ____☐ ____________
IC4256☐ J1 pad ____ = GPIO ____☐ ____________
IC4398☐ J1 pad ____ = GPIO ____☐ ____________
IC441211☐ J1 pad ____ = GPIO ____☐ ____________

Fifteen live channels, two readings each. Which channel of a chip carries which signal is deliberately left blank — that is the answer the tracing produces, not an input to it. The design fixes only which chip handles which pair of axes; the router chose the channels, and the only place that is written down is the copper. Fill the last two columns in and they become the pin map. The four IC3 inputs should all land on the same J1 pad, GPIO 21 — that is correct and is the point of the design, one pin disabling every axis. IC4 channel 4 is unused.

Also check on the bare board, while it is easy: every J7 position buzzes to J2's GND (the exact test v1.0 failed); each terminal's PUL−, DIR− and ENA− buzz to that same ground; and each of R1–R11's ground-side pads reaches it too.

⚠ Orientation — check before soldering J1

J1 footprint with the USB LEFT silkscreen marking
The only orientation cue on the board: J1 ESP32 / USB LEFT. Seat the module with its USB connector pointing at the left edge.

The socket takes the ESP32 either way round, and every pin is wrong if it is reversed. J1's thirty pads are identical ovals with no pin-1 marker — each chip got a square pad at pin 1, J2 and J7 got one, J1 did not. And the module covers that silkscreen once seated, so read it before the board disappears underneath.

Three checks, in this order. The module is never exposed until the first two pass.

  1. Continuity — nothing powered, no module. Buzz from J7 to find J1's ground pad, and from J2's +5V to find its supply pad. On a 30-pin DevKit, GND and VIN are adjacent, at positions 14 and 15 of the left column, so finding the board's two power pads side by side confirms you have the right end.
    Adjacency survives a flip — check the order too. VIN sits closer to the USB end than GND. So the 5V pad should be nearer the left edge, with ground one position further in. Reversed means the module would go in backwards.
    GND is not unique: a 30-pin DevKit has GND at position 14 in both columns, plus 3V3 at the bottom right. A single ground beep can mislead if you lose track of which column you are on — which is exactly why you check 5V as well.
  2. 5 V into J2 — still no module. J1's supply pad is on the same net, so it goes live. Walk a voltmeter across J1: one pad reads 5 V, one reads 0, the other twenty-eight read nothing. That finds both power pads with a meter rather than a beeper, and nothing is at risk with an empty socket.
  3. Seat the module, then read 3V3. Its 3V3 pin should sit at 3.3 V. This is the good final confirmation precisely because you did not wire it — it comes from the module's own regulator, so seeing it means the supply reached the correct pin.
Do not power a seated module until checks 1 and 2 pass. If the orientation is reversed, VIN lands on a GPIO and pushes 5 V into a 3.3 V pin before any reading warns you.
For v1.2: put a square pad at J1 pin 1. Every chip has one; the single part that would be destroyed by reversal does not.

Verification record

Checked three independent ways before ordering, deliberately not trusting any single view of the design:

MethodFound
Drill-coordinate parseJ1 rows 25.4 mm, pitch 2.54, span 35.56, drills 1.0 mm; all seven terminals 1.5 mm; board 120.00 × 80.00
IPC-D-356 netlist parseR1–R11 each on its own isolated net; C1–C4 across 5V/GND; no merged STEP/DIR nets; ENA reaching IC3 ×4 and IC4 ×1
OSH Park renderIndependent rendering by different software — passives on the underside, all footprints present
⚠ The lesson this revision taught, twice. The 3D render said nine resistors, then eleven, and one export contained none — while the design had all eleven the whole time, on the bottom layer. And an early check of mine read only the IPC 317 records, missing the 327 continuation records where the passives live, which produced a false alarm. Only the exported manufacturing data is authoritative, and it has to be parsed completely. Same failure mode as v1.0's J11 ground bus: a note saying "connected, confirmed by continuity" when the continuity had only ever been hole-to-hole.

Order

FabOSH Park — Lake Oswego, OR
OrderfB58RrsE, 2026-09-17
Spec120 × 80 mm, 2 layer, standard 1.6 mm, 1 oz
Cost$74.40 for 3, free shipping
Gerbers~/earthquake-sim/hardware/ss_stepper_board_v1_1/gerbers/ — the 858ca36c… package (08:14 export) is the one accepted